// -*- mode:c++ -*-
//
// 2009-2010 HIT Microelectronic Center all rights reserved
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
// Date: Dec. 2009
// Authors: Gou Pengfei

output header {{

#include <iostream>
    using namespace std;

    /**
     * Base class for instructions whose disassembly is not purely a
     * function of the machine instruction (i.e., it depends on the
     * PC).  This class overrides the disassemble() method to check
     * the PC and symbol table values before re-using a cached
     * disassembly string.  This is necessary for branches and jumps,
     * where the disassembly string includes the target address (which
     * may depend on the PC and/or symbol table).
     */
    class PCDependentDisassembly : public TRIPSStaticInst
    {
      protected:
        /// Cached program counter from last disassembly
        mutable Addr cachedPC;

        /// Cached symbol table pointer from last disassembly
        mutable const SymbolTable *cachedSymtab;

        /// Constructor
        PCDependentDisassembly(const char *mnem, MachInst _machInst,
                               OpClass __opClass)
            : TRIPSStaticInst(mnem, _machInst, __opClass),
              cachedPC(0), cachedSymtab(0)
        {
        }

        const std::string &
        disassemble(Addr pc, const SymbolTable *symtab) const;
    };

    /**
     * Base class for branches or calls (PC-relative control transfers) in TRIPS
     * PC in TRIPS ISA representes the block address which must be 128-bytes aligned.
     */
    class BwithOffset : public PCDependentDisassembly
    {
      protected:
        /// target address (signed) Displacement .
        int64_t _offset;

        /// predication bit
        uint8_t pr;

        /// Constructor.
        BwithOffset(const char *mnem, MachInst _machInst, OpClass __opClass)
            : PCDependentDisassembly(mnem, _machInst, __opClass),
              _offset(sext<20>(BRANCH_OFFSET) << 7 ), pr(PR)
        {
        		// Init _exitID
        		_exitID =EXIT;
        		switch(pr){
				case 0x0:_predication = Disable;break;
				case 0x2:_predication = PredUponFalse;break;
				case 0x3:_predication = PredUponTrue;break;
				default: _predication = Reserved; 
			}
        }

        Addr branchTarget(ThreadContext *tc) const;

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };

    /**
     * Base class for jumps (register-indirect control transfers).  In
     * the Mips ISA, these are always unconditional.
     */
    class BwithoutOffset : public PCDependentDisassembly
    {
      protected:
      
      /// predication bit
      uint8_t pr;
      
      public:
        /// Constructor
        BwithoutOffset(const char *mnem, MachInst _machInst, OpClass __opClass)
            : PCDependentDisassembly(mnem, _machInst, __opClass), pr(PR)
        {        		
        		// Init _exitID
        		_exitID = EXIT;
                	switch(pr){
				case 0x0:_predication = Disable;break;
				case 0x2:_predication = PredUponFalse;break;
				case 0x3:_predication = PredUponTrue;break;
				default: _predication = Reserved; 
			}
        }

        Addr branchTarget() const;

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    Addr
    BwithOffset::branchTarget(ThreadContext *tc) const
    {
    	Addr NextBlockPC = tc->getBlockPC();
        return NextBlockPC + _offset;
    }

    const std::string &
    PCDependentDisassembly::disassemble(Addr pc,
                                        const SymbolTable *symtab) const
    {
        if (!cachedDisassembly ||
            pc != cachedPC || symtab != cachedSymtab)
        {
            if (cachedDisassembly)
                delete cachedDisassembly;

            cachedDisassembly =
                new std::string(generateDisassembly(pc, symtab));
            cachedPC = pc;
            cachedSymtab = symtab;
        }

        return *cachedDisassembly;
    }

    std::string
    BwithOffset::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

        ccprintf(ss, "%-10s ", mnemonic);

        ss<<"";
        ccprintf(ss, "PR[%d]", pr);
        ss<<",";
        ccprintf(ss, "EXIT[%d]", _exitID);

        Addr target = pc + _offset;

        std::string str;
        if (symtab && symtab->findSymbol(target, str))
            ss << str;
        else
            ccprintf(ss, "0x%x", target);

        return ss.str();
    }

    std::string
    BwithoutOffset::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        std::stringstream ss;

        ccprintf(ss, "%-10s ", mnemonic);

        ss<<"";
        ccprintf(ss, "PR[%d] ", pr);
        ss<<",";
        ccprintf(ss, "EXIT[%d] ", _exitID);;

        ccprintf(ss, "target[Op0]");

        return ss.str();
    }
}};

def format BwithOffset(code, *opt_flags) {{
    opt_flags+=('IQOPerands', 'IsEDGE', 'IsControl','IsDirectControl',{'numConsumer':0},)
    iop = InstObjParams(name, Name, 'BwithOffset', code, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

def format BwithoutOffset(code, *opt_flags) {{
    opt_flags+=('IQOPerands', 'IsEDGE', 'IsControl','IsIndirectControl',{'numConsumer':0},)
    iop = InstObjParams(name, Name, 'BwithoutOffset', code, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};

def format syscall(code, *opt_flags) {{
    opt_flags+=('IsEDGE', 'IsControl','IQOPerands', {'numConsumer':0},)
    iop = InstObjParams(name, Name, 'BwithoutOffset', code, opt_flags)
    header_output = BasicDeclare.subst(iop)
    decoder_output = BasicConstructor.subst(iop)
    decode_block = BasicDecode.subst(iop)
    exec_output = BasicExecute.subst(iop)
}};
